The importance of storage systems has been continuously increasing in today's information society. In recent years, there has been a demand from the market for storage systems that are low-cost but still can achieve high performance in particular.
It is common in most storage systems that a host interface (hereinafter, “host I/F”) performs a data transfer process between a host computer and a cache memory while a disk interface (hereinafter, “disk I/F”) performs a data transfer process between a cache memory and a storage device. Note that, the host I/F and the disk I/F may be collectively referred to below as “protocol chip.”
The operation of storage systems, however, has various problems that are hard to solve using general-purpose protocol chips.
For example, when data is to be transferred from a storage device to a cache memory including an area where dirty data being update data yet to be written to a disk exists, the data needs to be transferred to the cache memory while avoiding the above area in order to avoid overwriting the dirty data with the transferred data. This case has a problem that a disk-read process needs to be performed a plurality of times. With respect to this problem, PTL 1 discloses a method for minimizing the number of disk-read processes. This method, called “bitmap staging”, uses the function of the data transfer controller called DMA (Direct Memory Access) to transfer only the necessary part of the data to the cache memory while selectively making a mask for the area where the dirty data is stored.
In addition, PTL 2 discloses a method for detecting a failure in storing data in its entirety in the storage apparatus, for example. This method uses DMA to append to the transfer data a special error detection code, called WRSEQ#, which is hard to provide with use of general-purpose protocol chips, and to check the appended special error detection code.
Besides the aforementioned examples, there are many storage systems that include an LSI (Large Scale Integration) with the DMA in addition to protocol chips, and that use the functions of DMA, such as dual-writing process to a cache memory, in order to achieve functions which are hard to provide with use of general-purpose protocol chips.